1. Field of the Invention
The present invention relates in general to integrated circuits and in particular to an integrated circuit structure in which respective gate and drain portions of a plurality of MOSFET cells are accessible through a top surface of a lateral structure.
2. Description of the Prior Art
Insulated gate devices such as power metal-oxide-semiconductor field-effect transistors (or MOSFETs) often comprise a plurality of interconnected cells distributed laterally over a top surface of a substrate, where each cell includes a source, channel and drain region arranged laterally along the top surface. The source regions are typically interconnected by a metallization layer overlying the top surface of the device. Such top surface interconnection can increase the cost of the insulated-gate device and utilize surface area which could be used for other structures.
FIG. 1 is a cross sectional view of a previous design in which plural identical MOSFET cells are fabrccated laterally along the top surface of a substrate 1 and are connected to external circuitry by ohmic contacts bonded to the top surface. Two such MOSFET cells are indicated at 10 and 20, respectively. The first MOSFET cell 10 includes a substrate-well contact 11 which is connected to a source terminal S.sub.1 through a first opening 17a provided in an insulating layer 17. One portion of the substrate-well contact 11 attaches to a p-type substrate contact region 15a at the top of a double diffused substrate-well 15. A second portion of the substrate-well contact 11 is bonded to the top of a n-type source region 16. A connecting region 15b extends laterally under the source region 16 from the substrate contact region 15a to a p-type channel region 15c which terminates at the top surface of the substrate 1. A silicon dioxide insulating layer 17 covers the channel region 15c and supports a polysilicon gate 18. The gate 18 is accessed by a gate terminal G.sub.1 extending upwardly from a gate contact 12. A drain terminal D.sub.1 rises vertically through a second opening 17b in the insulating layer 17 from a drain contact 13 that is bonded to the heavily doped (n+) surface of an n-type drain region 14. Contacts 11 and 13 are typically made of a metal such as a aluminum which bonds readily to the heavily doped surfaces of respective regions 15a, 16 and 14 and provides ohmic contact a the metal-semiconductor junctions.
The second MOSFET cell 20 is comprised of identical parts including a substrate-well contact 21 that is accessed through another opening 17c in the insulating layer by a second source terminal S.sub.2. A second gate contact 22 is provided coupled to a second gate terminal G.sub.2. A second drain contact 23 is accessed through the insulating layer 17 (opening 17d) by a second drain terminal D.sub.2. The substrate 1 also includes a drift region 2 (n-), portions of which project to the top surface between the channel and drain regions of each MOSFET cell; an epitaxial layer 3 (p--), a bulk layer 4 (p+) and a substrate contact 5 at the bottom surface of the substrate as shown in FIG. 1. The substrate contact 5 is typically coupled to ground through a substrate terminal SBST.
In many previous circuits, the first and second source terminals, S.sub.1 and S.sub.2 are connected to a common point, such as ground, by a conductive metallization layer represented by a ground bus 30 in FIG. 1. This metallization layer is often insulatively disposed over the top surface of the device and connected to individual source regions through openings (e.g. the first and third openings, 17a and 17c) provided in one or more insulating layers. As previously mentioned, this arrangement can increase the cost of the device and also utilize space needed for other structural features.
For situations where multiple semiconductor cells, such as MOEFET cells 10 and 20 of FIG. 1, are dispersed across the entire face of an integrated circuit chip (IC), it is often necessary to provide a plurality of inter-cell coupling layers which span across and consume major portions of the surface area available at the top of the IC. The inter-cell coupling layers are typically formed in separate fabrication steps wherein a first insulation layer (e.g. oxide layer) is deposited on the top face of the IC, through-holes are etched at required locations to permit connection to semiconductor regions of the substrate, a first metal layer (e.g. aluminum) is deposited on the first insulation layer in a predetermined pattern to connect selected substrate regions one to the other, a second insulation layer is deposited over the first metal layer, through-holes are etched in accurate alignment with the through holes of the first insulation layer, and a second metal layer is deposited across the top face of the IC to provide additional intercoupling of cells dispersed aross the IC. The deposition of each set of metal connecting layer and oxide insulating layer adds to the cost of the final IC and increases the probability that a fault will develop during fabrication thereby lowering the manufacturing yield. An inter-cell coupling arrangement which obviates the need for at least one set of metal and insulating layers would reduce cost, increase manufacturing yield, and permit denser circuit packing by freeing chip surface areas previously occupied by the prior art through-hole connections provided through the insulation layers for accessing the top surface of the semiconductor substrate.